Space time block codes
Space time block code (STBC) based IP cores provide drag and drop type IPs for configuring the STBC communication system. The generated VHDL codes would directly fit in FPGA design flow of Xilinx’s and Altera’s tools. The IPs are optimized for FPGAs however they can also be used for ASIC development.
Please contact ip@nsscomm.com for more details.
|
