NSS Communications
Home | Contact Us
Wide band DDC (NSSWBDDC)

Wide band DDC offered by NSS can be very useful front end for wide band communication and RADAR signal processing applications targeted for both ASIC/FPGA platforms. The cores are optimized and offered in different versions to see that designer can pick configuration of his interest based on the requirements. The current version of the DDC core is offered keeping the broad needs of software defined radio based applications.

Legacy DDC cores generally available in market would give a general DDC IP which doesn’t become the best fit for most of the applications. Several times you will be paying for FPGA resources even though you don’t need such features in your applications. In addition lot many run time configuration features which are required in current SDRs are not provided by these cores.

NSSWBDDC IP core allows the designer to select the required configuration mode and associated parameters. The generated code will be very specific to your application and highly optimized in terms of area and speed. Low area design automatically yields to low power, which is the most desirable feature in mobile applications.

The IP core can be generated in one of the following mode.

a) Single channel (fixed NCO)

This has fixed parameters such as the clock frequency, input sample rate, decimation factor and filter characteristics etc. So user will choose the decimation factor and decide what filter characteristics would suit him. Based on the options the core will be generated with synthesizable files and simulation models.

b) Single channel (variable NCO)

In this mode the user need to enter the range of Local oscillator values, based on that the NCO core will be generated. Remaining parameters will be considered fixed such as clock frequency, input sample rate, filter characteristics and fixed decimation value.

c) Multi channel DDC

In this mode the IP can be deployed catering to predefined number of parallel channels each can be configured in either in fixed NCO mode or variable NCO mode.

The core supports decimation rates 2,3,4,5,6,7,8,9,10,11,12,13,14,15 and 16.

Contact ip@nsscomm.com for more information, FPGA performance benchmarks and pricing information.


© Copyright reserved @ NSS Communications, 2010