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Pipelined CORDIC

Historically CORDIC is used as low area alternative solution for trigonometric function computation and complex mathematical operations. The CORDIC algorithm is multiplier less architecture, hence became very much useful in both FPGA and ASIC based designs. However CORDIC being serial algorithm, to compute each output value for a given input value, takes N number of clock cycles. The N value depends on the number of bit accuracy required. Hence effectively the trigonometric function is computed at the rate of fclk/N. Where fclk is the clock frequency of the CORDIC datapath. This is the drawback of the conventional CORDIC design approach.

NSS’s pipelined CORDIC algorithm is speed optimized IP core at the expense of using additional registers. However as FPGAs consists of abundance of registers most of the applications can use pipelined CORDIC. In the pipelined CORDIC’s serial data path is unrolled to parallel implementation with pipeline inserted at every stage. This results in enormous speed improvement. In pipelined CORDIC case, the trigonometric function can be computed at fclk (that is single clock cycle for each output computation). This core observed to work at 200 MHz clock in virtex-4 and Virtex-5 devices.


  • Digital carrier generation in communication applications (NCO)
  • Carrier frequency offset estimation in receiver
  • Performing sqroot and few other arithmetic operations


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