Encoders and Decoders
- LDPC Encoder and Decoder IP Cores
- Viterbi encoder and Decoder
- Reed Solomon Encoder and decoders
LDPC Encoder and Decoder IP Cores:
Rigorous research and efforts are put into VLSI/ASIC/FPGA realizations of the decoders and encoders. Concentrating on the decoders, there are different issues to be considered in the realization like, serial, parallel or semi-parallel architectures, edge memory requirement, processing unit complexity (for check node processing), and so on. Serial architecture consumes less amount of silicon area but takes a lot of time for processing. So this architecture may not produce the best performance results. Fully parallel architecture consists of enough number of functional units and produces the results in short span of time, but requires a huge amount of silicon area for realization. Semi-parallel architecture is the compromise between these two. By observing the independency among the computation units we designed a semi-parallel architecture which is conservative in the area of silicon as well as in the processing time for decoding. We have several variants of algorithms to decode LDPC codes.
Viterbi encoder and Decoder:
The Block Viterbi Decoder IP core is a parameterizable core for decoding different combinations of convolutionally encoded sequences. The decoder core supports both hard-decision and soft-decision decoding. The core can operate in continuous or block mode, whichever is required by the channel. The parameters of the core are configuration through GUI (optional). The design is highly optimized for FPGA based implementation for high speeds.
The design has parameterizable traceback depth to suite different applications. Block RAM is used for saving the partially processed data which gives higher speeds and area efficiency. Branch Metric Unit (BMU) and Add Compare Select Unit (ACSU) are designed to suite both hard and soft decision. Full design is controlled through a state machine. On chip debugging of the core can be done on PC through chipscope tool.
Reed-Solomon encoder/decoder:
The Reed-Solomon encoder/decoder IP core is a highly versatile IP core for high speed encoding and decoding of the ubiquitous Reed-Solomon Forward Error Correction (FEC) code. This core can be used in a wide variety of data storage and transmission applications, such as Software Defined Radios, Broadband networks, various kinds of magnetic storage, digital subscriber lines and satellite communications.
The IP core uses a single clock for synchronous purposes. The code flags the failures and counts the number of errors corrected and possesses 64 bits error correcting capability. The number of errors corrected, symbol size and codeword length are programmable. The code also supports continuous input data stream without gap between code blocks. The architecture is highly optimized for FPGA implementation.
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