Embedded Security
AES, DES, IDEA and XTEA
Encryption/Decryption IP Cores are developed keeping all class of applications in consideration. All the AES, DES, IDEA and XTEA algorithms are available in two forms. The high speed version of the cores are fully pipelined architectures for high throughput networking applications. Whereas low power version of IP cores are designed for energy sensitive wireless communication applications. The low power architecture also occupies less number of FPGA cells. Both these types of architectures are optimized for FPGA based applications.
Send enquiry to ip@nsscomm.com for more details.
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