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DSP data compressor

In several FPGA signal processing applications the data need to be moved from one FPGA node to another. The inter-chip and inter-board communication speeds limit the throughput of the whole application.

We provide solution for handling this problem with hardware implemented compression and decompression algorithm.

This IP occupies only 6% of area for compression and 10% of area for decompression on Virtex-5 Sx95 FPGA. Typically this algorithm can achieve compression ratio up to 5 depending on the nature of the data.


  • Multi FPGA DSP platforms
  • On chip logic analyzers
  • FPGA based instrumentation


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